1). Field of the Invention
The present invention relates to a method of forming a protective conductive structure on an integrated circuit package interconnection. More specifically, the present invention relates to such a conductive structure which is plated for low resistivity and corrosion protection reasons.
2). Discussion of Related Art
The manufacture of a semiconductor chip involves the formation of an integrated circuit on a wafer. Bond pads are formed on the wafer and are connected to the integrated circuit. Conductive structures such as controlled collapse chip connect (C4) bumps are then formed on the wafer so that each bump is electrically connected to a respective bond pad. The wafer is then cut into a number of semiconductor dice. Such a die is then mounted to a package substrate with the bumps located between the die and the package substrate. FIG. 1 shows such a die 1 which is cut from a wafer and mounted to a substrate 2 by an array of C4 bumps 3.
An integrated circuit within the wafer is usually tested for logic functionality and speed before being cut into respective dice.
One method of testing an integrated circuit within a wafer is shown in FIG. 2. A probe card 4 is brought into contact with the wafer 1. The probe card 4 has a number of contacts 5, each making contact with a respective unreflowed bump 3 on the wafer 1. The probe card 4 is connected to an electrical tester 6. The electrical tester 6 is then operated to test the integrated circuit with an interface between the contacts 5 and the bumps 3 providing a link between the electrical tester and the integrated circuit.
The bumps 3 are often made primarily of lead. These lead bumps are prone to corrosion, especially during thermal shock or elevated temperature tests of the wafer 1. Corrosion of the lead bumps results in a layer comprising of lead oxides and contaminants on the lead bumps having relatively low conductivities and leading to a relatively high contact resistance between the contacts 5 of the probe card 4 and lead bumps 3. A high contact resistance may result in the electrical tester not accurately testing the speed or functionality of the integrated circuit.
The invention provides a method of forming a conductive structure on an integrated circuit substrate. A metal bump, of a first material, is structured on the substrate so that the metal bump electrically contacts a metal part on the substrate. A protective layer is formed on the metal bump. The first material has a first conductivity. The protective layer is of a second material which has a second conductivity which is more than the first conductivity.